In a semiconductor device, different conductive or semiconductive layers can be connected to one another by contacts and/or vias. Contacts and/or vias can include contact holes that extend through one or more insulating layers. Conventionally, contacts can connect a substrate to a conductive or semiconductive layer, while a via can connect two different conductive or semiconductive layers to one another.
One concern with certain contact structures can be the alignment of a contact with a lower conducting layer. Because a contact is usually formed by etching a hole through an insulating layer to an underlying conductive or semiconductive layer, it is desirable for the etched hole to be situated directly over the desired contact location in the lower conducting layer. Further, it may be desirable to ensure that a contact hole can be sufficiently insulated from other conductive lines. For example, in the case of semiconductor devices having insulated gate field effect transistors (IGFETs), such as metal-oxide-semiconductor FETs (MOSFETs), it is desirable to have a contact hole aligned with a source or drain, but at the same time, be sufficiently insulated from a gate conductor.
To better understand the formation of certain integrated circuit structures, including contacts and contact holes, a conventional self-aligned contact (SAC) approach is set forth in FIGS. 4A and 4B. FIG. 4A shows a semiconductor device 400 that includes a semiconductor substrate 402. Conductive structures 404-0 and 404-1 may be formed on a substrate 402 having surrounding insulating structures that may allow for self-aligned contacts. In the particular example of FIGS. 4A and 4B, conductive structures 404-0 and 404-1 may be typical insulated gate field effect transistor (IGFET) devices that include a conductive gate (406-0 and 406-1), a top insulator (408-0 and 408-1), as well as insulating sidewalls (410).
An insulator layer 412 may be formed over conductive structures 404-0 and 404-1. In one particular example, an insulator layer 412 may comprise a layer of doped silicon dioxide, such as borophosphosilicate glass (BPSG) or phosphosilicate glass (PSG), for example.
FIG. 4A shows a semiconductor device 400 following a lithography step that develops a pattern of photoresist. More particularly, FIG. 4A shows an example of a lithography step for a process aimed at wavelengths of 248 nm or larger, and includes developing a layer photoresist 414 having a thickness of about 6500 angstroms (Å). A bottom anti-reflective coating (BARC) 416, formed from a light absorbing polymer or the like, can be formed below photoresist layer 414. Development of a photoresist layer 414 may result in mask opening 418.
Conventionally, a contact hole may then be etched through a BARC layer 416 and insulator layer 412. A conventional semiconductor device following a contact hole etch is shown in FIG. 4B. As shown in FIG. 4B, following a conventional etching step, while some of the photoresist layer 414 may have been removed, sufficient photoresist exists to continue to mask insulator layer 412, and thus form a contact hole having an acceptable size. Whether a contact hole may be of an acceptable size can be determined by measuring the contact hole.
It is noted that a conventional approach, such as that shown in FIGS. 4A and 4B may be a single etch step. That is, once an etch mask is formed a single etching operation may form a contact hole.
While a conventional approach, such as that shown in FIGS. 4A and 4B, may be appropriate for photoresist layers having a thickness greater than about 3000 Å, at a smaller resist thickness such approaches may have drawbacks.
A drawback to conventional approaches at a smaller resist thickness is shown in FIGS. 5A to 5C. FIG. 5A shows a semiconductor device 500 that includes some of the same general features as FIGS. 4A and 4B, including a semiconductor substrate 502, conductive structures (504-0 and 504-1) with conductive gates (506-0 and 506-1), a top insulator (508-0 and 508-1), insulating sidewalls 510, insulator layer 512, a layer photoresist 514, a bottom anti-reflective coating (BARC) 516, and a mask opening 518.
The conventional example of FIGS. 5A to 5C differs from that of FIGS. 4A and 4B in that a higher resolution photolithography method is used. Such a higher resolution approach, due to more limited fields of focus, can include a photoresist layer 514 having a thickness of about 3500 Å or less. Unfortunately, a reduction in thickness may not be compatible with some conventional etching approaches. This is illustrated in FIGS. 5B and 5C.
In FIG. 5B, a semiconductor device 500 is shown, part way through a conventional single step etching process. It is shown that while the etching of a contact hole has not been completed, a photoresist layer 514, due to its smaller thickness, has been substantially removed. Without a photoresist layer 514 intact, etching may proceed unconstrained. Consequently, as shown in FIG. 5C, a resulting contact hole may be greater than a desired size, shown by dashed lines.
U.S. Pat. No. 6,214,743, issued to Qiao et al on Apr. 10, 2001, entitled METHOD AND STRUCTURE FOR MAKING SELF-ALIGNED CONTACTS, shows a method of forming a self-aligned contact that includes a two step etch process with a “hard” etch mask. One particular example of such a two step approach is shown in FIGS. 6A to 6C. FIG. 6A shows a semiconductor device 600 that includes some of the same general features as FIGS. 4A and 4B, including a semiconductor substrate 602, conductive structures (604-0 and 604-1) with conductive gates (606-0 and 606-1), a top insulator (608-0 and 608-1), insulating sidewalls 610, insulator layer 612, a layer of photoresist 614, a bottom anti-reflective coating (BARC) 616, and a mask opening 618. Unlike the conventional case as described in FIGS. 4A to 4C, the semiconductor device 600 of FIGS. 6A to 6C may include a hard mask layer 622.
As shown in FIG. 6A, a photoresist layer 614 may be patterned. Then, as shown in FIG. 6B, a hard mask layer 622 may be patterned with a layer of photoresist 614 as a mask. FIG. 6C shows how at a thinner resist thickness (less than 4000 Å), etching through a BARC layer 616 and a hard mask layer 622, may consume all or most of a photoresist layer 614.
Following an initial patterning of a hard mask layer 622, a semiconductor device 600 may be cleaned. Such a cleaning step may include removing a photoresist layer, by an ashing step, or the like. This may or may not be followed by a wet etch. A method may continue by etching with a patterned hard mask layer 622 as an etch mask. A resulting contact hole 620 is shown in FIG. 6C.
Thus, in the example of FIGS. 6A to 6C, a contact formation method may include particular steps. A first step may pattern a hard mask layer 622. A second step may include cleaning to remove a photoresist layer and expose a hard mask. A third step may include etching with a hard mask layer 622.
Alternative conventional approaches to etching contact holes have been proposed. Such approaches attempt to increase selectivity between a photoresist layer and an underlying insulator layer. As a first example, a plasma etching process may employ hexafluorobutadiene (C2F6) and oxygen (O2) as reactant gases. As a second example, a plasma etching process may employ octafluorocyclobutane (C4F8), carbon monoxide (CO) and argon as reactant gases. Such approaches may involve greater costs as the gases C2F6 and C4F8 may be more expensive than other known etch gases, such as carbon tetrafluoride (CF4) and/or tetrafluoroethane (C2H2F4). Still further, such conventional approaches may require particular chamber sensors that can also increase costs.
In light of the above discussion, it would be desirable to arrive at some way of etching contact holes with a smaller resist thickness that does not require as many process steps as conventional approaches. It would also be desirable to arrive at a contact hole etching method that may be less expensive to implement than conventional etches that include gases C2F6 and C4F8 and etch gases.